Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 687

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Integrated Intel High Definition Audio Controller Registers
17.1.1.4 PCISTS—PCI Status Register
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(Intel
Offset Address: 06h–07h
Default Value:
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
17.1.1.5 RID—Revision Identification Register
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(Intel
Offset:
Default Value:
Bit
7:0
17.1.1.6 PI—Programming Interface Register
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(Intel
Offset:
Default Value:
Bit
7:0
Datasheet
High Definition Audio Controller—D27:F0)
0010h
Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.
SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.
Received Master Abort (RMA) — R/WC. Software clears this bit by writing a 1 to it.
0 = No master abort received.
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1 = The Intel High Definition Audio controller sets this bit when, as a bus master, it
receives a master abort. When set, the Intel
clears the run bit for the channel that received the abort.
Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0.
Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. Does not apply. Hardwired to 0.
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Does not apply. Hardwired to 0.
Reserved.
66 MHz Capable (66MHZ_CAP) — RO. Does not apply. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 1. Indicates that the controller
contains a capabilities pointer list. The first item is pointed to by looking at
configuration offset 34h.
Interrupt Status (IS) — RO.
0 = This bit is 0 after the interrupt is cleared.
1 = This bit is 1 when the INTx# is asserted.
Note that this bit is not set by an MSI.
Reserved.
High Definition Audio Controller—D27:F0)
08h
See bit description
Revision ID — RO. See the Intel
of the RID Register.
High Definition Audio Controller—D27:F0)
09h
00h
Programming Interface — RO.
Attribute:
Size:
Description
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High Definition Audio controller
Attribute:
Size:
Description
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6 Series Chipset Specification Update for the value
Attribute:
Size:
Description
RO, R/WC
16 bits
RO
8 Bits
RO
8 bits
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