Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 449

LPC Interface Bridge Registers (D31:F0)
13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address: 04h
Default Value:
Lockable:
Bit
15:10
9
8
7
6
5
4
3
2
1
0
13.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address: 06h
Default Value:
Lockable:
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
14
13
12
Datasheet
05h
–
0007h
No
Reserved
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response Enable (PERE) — R/W.
0 = No action is taken when detecting a parity error.
1 = Enables the PCH LPC bridge to respond to parity errors detected on backbone
interface.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.
I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.
07h
–
0210h
No
Detected Parity Error (DPE) — R/WC. Set when the LPC bridge detects a parity
error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is
0.
0 = Parity Error Not detected.
1 = Parity Error detected.
Signaled System Error (SSE)— R/WC. Set when the LPC bridge signals a system
error to the internal SERR# logic.
Master Abort Status (RMA) — R/WC.
0 = Unsupported request status not received.
1 = The bridge received a completion with unsupported request status from the
backbone.
Received Target Abort (RTA) — R/WC.
0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
Attribute: R/W, RO
Size: 16-bit
Power Well: Core
Description
Attribute: RO, R/WC
Size: 16-bit
Power Well: Core
Description
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