Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 104

Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 4 of 6)
Signal Name
7
GPIO8 Suspend
7
GPIO15 Suspend
GPIO24 Suspend
7
GPIO27 (Non-Deep
S4/S5 mode)
7
GPIO27 (Deep S4/S5
mode)
GPIO28 Suspend
GPIO57 Suspend
GPIO0
8
GPIO[17,7,6,1]
GPIO35
GPIO50
GPIO[55,53,51]
GPIO52
GPIO54
GPIO[71:68]
SPI_CS0#
7
SPI_CS1#
7
SPI_MOSI
SPI_CLK
6
CL_CLK1 Suspend
6
CL_DATA1 Suspend
6
CL_RST1# Suspend
104
Power During Immediately
1
Plane Reset
UnMultiplexed GPIO Signals
High
Low
Low
DSW High-Z
DSW High-Z
High
Low High-Z (Input)
Multiplexed GPIO Signals used as GPIO only
High-Z
Core High-Z (Input)
(Input)
Core High-Z
Core Low
Core High-Z
Core High
Core High-Z
Core High-Z
Core High-Z
SPI Interface
18
ASW High
18
ASW High
18
ASW Low
18
ASW Low
Controller Link
13
High/Low
13
High/Low
Low
C-x
1
after Reset states
High Defined
Low Defined
Low Defined
High-Z High-Z
High-Z High-Z
Low Low
Defined
Defined
High-Z High-Z
Low Defined
High-Z High-Z
High High
High-Z High-Z
High-Z High-Z
High-Z High-Z
High Defined
High Defined
Low Defined
Low Running
13
High/Low Defined
13
High/Low Defined
High Defined
PCH Pin States
S0/S1 S3 S4/S5
Defined Defined Defined
Defined Defined Defined
Defined Defined Defined
High-Z High-Z High-Z
High-Z High-Z High-Z
Low Low
Defined Defined Defined
Defined Off
High-Z Off
Defined Off
High-Z Off
High Off
High-Z Off
High-Z Off
High-Z Off
Defined Defined Defined
Defined Defined Defined
Defined Defined Defined
Running Defined Defined
Defined Defined Defined
Defined Defined Defined
High High
Datasheet
Low
Off
Off
Off
Off
Off
Off
Off
Off
High