Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 540

13.9.9 TCO_WDCNT—TCO Watchdog Control Register
Offset Address: TCOBASE + 0Eh
Default Value:
Power Well:
Bit
The BIOS or system management software can write into this register to indicate more
details on the boot progress. The register will reset to 00h based on a RSMRST# (but
7:0
not PLTRST#). The external microcontroller can read this register to monitor boot
progress.
13.9.10 SW_IRQ_GEN—Software IRQ Generation Register
Offset Address: TCOBASE + 10h
Default Value:
Power Well:
Bit
7:2 Reserved
IRQ12_CAUSE — R/W. When software sets this bit to 1, IRQ12 will be asserted. When
1
software sets this bit to 0, IRQ12 will be deasserted.
IRQ1_CAUSE — R/W. When software sets this bit to 1, IRQ1 will be asserted. When
0
software sets this bit to 0, IRQ1 will be deasserted.
13.9.11 TCO_TMR—TCO Timer Initial Value Register
I/O Address:
Default Value:
Lockable:
Bit
15:10 Reserved
TCO Timer Initial Value — R/W. Value that is loaded into the timer each time the
TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not
be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows
9:0
timeouts ranging from 1.2 second to 613.8 seconds.
NOTE: The timer has an error of ±1 tick (0.6 S).
The TCO Timer will only count down in the S0 state.
540
00h
Resume
03h
Core
TCOBASE +12h
0004h
No
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 16-bit
Power Well: Core
Description
Datasheet