Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 451

LPC Interface Bridge Registers (D31:F0)
13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah
Default Value:
Bit
7:0
13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh
Default Value:
Bit
7:0
13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh
Default Value:
Bit
7:3
2:0
13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh
Default Value:
Bit
7
6:0
Datasheet
01h
Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC
bridge.
01h = PCI-to-ISA bridge.
06h
Base Class Code — RO. 8-bit value that indicates the type of device for the LPC
bridge.
06h = Bridge device.
00h
Master Latency Count (MLC) — Reserved.
Reserved.
80h
Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
Header Type — RO. This 7-bit field identifies the header layout of the configuration
space.
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
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