Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 892

23.4.2 H_CSR—Host Control Status
(MEI MMIO Register)
Address Offset: MEI1_MBAR + 04h
Default Value:
Bit
Host Circular Buffer Depth (H_CBD) — RO. This field indicates the maximum
number of 32 bit entries available in the host circular buffer (H_CB). Host software uses
this field along with the H_CBRP and H_CBWP fields to calculate the number of valid
entries in the H_CB to read or # of entries available for write.
31:24
NOTE: This field is implemented with a "1-hot" scheme. Only one bit will be set to a 1
Host CB Write Pointer (H_CBWP). Points to next location in the H_CB for host to
write the data. Software uses this field along with H_CBRP and H_CBD fields to
23:16
calculate the number of valid entries in the H_CB to read or number of entries available
for write.
Host CB Read Pointer (H_CBRP). Points to next location in the H_CB where a valid
data is available for embedded controller to read. Software uses this field along with
15:8
H_CBWR and H_CBD fields to calculate the number of valid entries in the host CB to
read or number of entries available for write.
7:5 Reserved Must be programmed to zero
Host Reset (H_RST). Setting this bit to 1 will initiate a Intel MEI reset sequence to
4 get the circular buffers into a known good state for host and ME communication. When
this bit transitions from 0 to 1, hardware will clear the H_RDY and ME_RDY bits.
3 Host Ready (H_RDY). This bit indicates that the host is ready to process messages.
Host Interrupt Generate (H_IG). Once message(s) are written into its CB, the host
sets this bit to one for the HW to set the ME_IS bit in the ME_CSR and to generate an
2
interrupt message to ME. HW will send the interrupt message to ME only if the ME_IE is
enabled. HW then clears this bit to 0.
Host Interrupt Status (H_IS). Hardware sets this bit to 1 when ME_IG bit is set to 1.
1
Host clears this bit to 0 by writing a 1 to this bit position. H_IE has no effect on this bit.
Host Interrupt Enable (H_IE). Host sets this bit to 1 to enable the host interrupt
0
(INTR# or MSI) to be asserted when H_IS is set to 1.
23.4.3 ME_CB_RW—ME Circular Buffer Read Window
(MEI MMIO Register)
Address Offset: MEI1_MBAR + 08h
Default Value:
Bit
ME Circular Buffer Read Window Field (ME_CB_RWF). This bit field is for host to
read from the ME Circular Buffer. The ME's circular buffer is located at the ME
subsystem address specified in the ME CB Base Address register. This field is read only,
31:0
writes have no effect. Reads to this register will increment the ME_CBRP as long as
ME_RDY is 1. When ME_RDY is 0, reads to this register have no effect, all 1s are
returned, and ME_CBRP is not incremented.
892
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
02000000h
at a time. Each bit position represents the value n of a buffer depth of (2^n).
For example, when bit# 1 is 1, the buffer depth is 2; when bit#2 is 1, the buffer
depth is 4, etc. The allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128.
FFFFFFFFh
Attribute: RO
Size: 32 bits
Description
Attribute: RO
Size: 32 bits
Description
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