Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 371

Chipset Configuration Registers
10.1.19 LCAP—Link Capabilities Register
Offset Address: 21A4–21A7h
Default Value:
Bit
31:18
17:15
(Desktop
Only)
17:15
(Mobile
Only)
14:12
11:10
9:4
3:0
10.1.20 LCTL—Link Control Register
Offset Address: 21A8–21A9h
Default Value:
Bit
15:8
7
6:2
1:0
Datasheet
00012C42h
Reserved
Reserved
L1 Exit Latency (EL1) — RO. L1 is supported on DMI.
L0s Exit Latency (EL0) — R/WO. This field indicates that exit latency is 128 ns to
less than 256 ns.
Active State Link PM Support (APMS) — R/WO. Indicates that L0s and L1 are
supported on DMI.
Maximum Link Width (MLW) — RO. Indicates the maximum link width is 4 ports.
Maximum Link Speed (MLS) — RO. Indicates the link speed is 5.0 Gb/s.
0000h
Reserved
Extended Synch (ES) — R/W. When set, forces extended transmission of FTS
ordered sets when exiting L0s prior to entering L0.
Reserved
Active State Link PM Control (ASPM) — R/W. Indicates whether DMI should enter
L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
Attribute: R/WO, RO
Size: 32-bit
Description
Attribute: R/W
Size: 16-bit
Description
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