Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 243

Functional Description
5.24.1.2 Descriptor Mode
Descriptor Mode is required for all SKUs of the PCH. It enables many new features of
the chipset:
• Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software
• Intel Active Management Technology
• Intel Management Engine Firmware
• PCI Express* root port configuration
• Supports up to two SPI components using two separate chip select pins
• Hardware enforced security restricting master accesses to different regions
• Chipset Soft Strap regions provides the ability to use Flash NVM as an alternative to
hardware pull-up/pull-down resistors for the PCH and processor
• Supports the SPI Fast Read instruction and frequencies of up to 50 MHz
• Support Single Input, Dual Output Fast read
• Uses standardized Flash Instruction Set
5.24.1.2.1 SPI Flash Regions
In Descriptor Mode the Flash is divided into five separate regions:
Region
0
1
2
3
4
Only three masters can access the four regions: Host processor running BIOS code,
Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and
Management Engine. The only required region is Region 0, the Flash Descriptor. Region
0 must be located in the first sector of Device 0 (Offset 0).
Datasheet
Content
Flash Descriptor
BIOS
Management Engine
Gigabit Ethernet
Platform Data
243