Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 767

PCI Express* Configuration Registers
19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/
F7/F6/F7)
Address Offset: 28h–2Bh
Default Value:
Bit
31:0
19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/
F7/F6/F7)
Address Offset: 2Ch–2Fh
Default Value:
Bit
31:0
19.1.20 CAPP—Capabilities List Pointer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 34h
Default Value:
Bit
7:0
Datasheet
00000000h
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the
prefetchable address base.
00000000h
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the
prefetchable address limit.
40h
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at 40h in configuration space.
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
Attribute: RO
Size: 8 bits
Description
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