Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 25

21.1.4 FADDR—Flash Address Register
(SPI Memory Mapped Configuration Registers) ......................................... 813
21.1.5 FDATA0—Flash Data 0 Register
(SPI Memory Mapped Configuration Registers) ......................................... 814
21.1.6 FDATAN—Flash Data [N] Register
(SPI Memory Mapped Configuration Registers) ......................................... 814
21.1.7 FRAP—Flash Regions Access Permissions Register
(SPI Memory Mapped Configuration Registers) ......................................... 815
21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register
(SPI Memory Mapped Configuration Registers) ......................................... 816
21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register
(SPI Memory Mapped Configuration Registers) ......................................... 816
21.1.10FREG2—Flash Region 2 (Intel® ME) Register
(SPI Memory Mapped Configuration Registers) ......................................... 817
21.1.11FREG3—Flash Region 3 (GbE) Register
(SPI Memory Mapped Configuration Registers) ......................................... 817
21.1.12FREG4—Flash Region 4 (Platform Data) Register
(SPI Memory Mapped Configuration Registers) ......................................... 818
21.1.13PR0—Protected Range 0 Register
(SPI Memory Mapped Configuration Registers) ......................................... 818
21.1.14PR1—Protected Range 1 Register
(SPI Memory Mapped Configuration Registers) ......................................... 819
21.1.15PR2—Protected Range 2 Register
(SPI Memory Mapped Configuration Registers) ......................................... 820
21.1.16PR3—Protected Range 3 Register
(SPI Memory Mapped Configuration Registers) ......................................... 820
21.1.17PR4—Protected Range 4 Register
(SPI Memory Mapped Configuration Registers) ......................................... 821
21.1.18SSFS—Software Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers) ......................................... 822
21.1.19SSFC—Software Sequencing Flash Control Register
(SPI Memory Mapped Configuration Registers) ......................................... 823
21.1.20PREOP—Prefix Opcode Configuration Register
(SPI Memory Mapped Configuration Registers) ......................................... 824
21.1.21OPTYPE—Opcode Type Configuration Register
(SPI Memory Mapped Configuration Registers) ......................................... 824
21.1.22OPMENU—Opcode Menu Configuration Register
(SPI Memory Mapped Configuration Registers) ......................................... 825
21.1.23BBAR—BIOS Base Address Configuration Register
(SPI Memory Mapped Configuration Registers) ......................................... 826
21.1.24FDOC—Flash Descriptor Observability Control Register
(SPI Memory Mapped Configuration Registers) ......................................... 826
21.1.25FDOD—Flash Descriptor Observability Data Register
(SPI Memory Mapped Configuration Registers) ......................................... 827
21.1.26AFC—Additional Flash Control Register
(SPI Memory Mapped Configuration Registers) ......................................... 827
21.1.27LVSCC— Host Lower Vendor Specific Component Capabilities Register
(SPI Memory Mapped Configuration Registers) ......................................... 827
21.1.28UVSCC— Host Upper Vendor Specific Component Capabilities Register
(SPI Memory Mapped Configuration Registers) ......................................... 829
21.1.29FPB — Flash Partition Boundary
(SPI Memory Mapped Configuration Registers) ......................................... 830
21.1.30SRDL — Soft Reset Data Lock
(SPI Memory Mapped Configuration Registers) ......................................... 831
21.1.31SRDC — Soft Reset Data Control
(SPI Memory Mapped Configuration Registers) ......................................... 831
21.1.32SRD — Soft Reset Data
(SPI Memory Mapped Configuration Registers) ......................................... 831
21.2 Flash Descriptor Records .................................................................................. 832
21.3 OEM Section ................................................................................................... 832
21.4 GbE SPI Flash Program Registers....................................................................... 832
21.4.1 GLFPR –Gigabit LAN Flash Primary Region Register
(GbE LAN Memory Mapped Configuration Registers) .................................. 833
21.4.2 HSFS—Hardware Sequencing Flash Status Register
(GbE LAN Memory Mapped Configuration Registers) .................................. 833
21.4.3 HSFC—Hardware Sequencing Flash Control Register
(GbE LAN Memory Mapped Configuration Registers) .................................. 835
Datasheet 25