Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 930

23.10.1 KTRxBR—KT Receive Buffer Register (KT—D23:F3)
Address Offset: 00h
Default Value:
This implements the KT Receiver Data register. Host access to this address, depends on
the state of the DLAB bit (KTLCR[7]). It must be 0 to access the KTRxBR.
RxBR:
Host reads this register when FW provides it the receive data in non-FIFO mode. In
FIFO mode, host reads to this register translate into a read from ME memory (RBR
FIFO).
Bit
7:0
23.10.2 KTTHR—KT Transmit Holding Register (KT—D23:F3)
Address Offset: 00h
Default Value:
This implements the KT Transmit Data register. Host access to this address, depends on
the state of the DLAB bit (KTLCR[7]). It must be 0 to access the KTTHR.
THR:
When host wants to transmit data in the non-FIFO mode, it writes to this register. In
FIFO mode, writes by host to this address cause the data byte to be written by
hardware to ME memory (THR FIFO).
Bit
7:0
23.10.3 KTDLLR—KT Divisor Latch LSB Register (KT—D23:F3)
Address Offset: 00h
Default Value:
This register implements the KT DLL register. Host can Read/Write to this register only
when the DLAB bit (KTLCR[7]) is 1. When this bit is 0, Host accesses the KTTHR or the
KTRBR depending on Read or Write.
This is the standard Serial Port Divisor Latch register. This register is only for software
compatibility and does not affect performance of the hardware.
Bit
7:0
930
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
00h
Receiver Buffer Register (RBR)— RO. Implements the Data register of the Serial
Interface. If the Host does a read, it reads from the Receive Data Buffer.
00h
Transmit Holding Register (THR)— WO. Implements the Transmit Data register of
the Serial Interface. If the Host does a write, it writes to the Transmit Holding
Register.
00h
Divisor Latch LSB (DLL)— R/W. Implements the DLL register of the Serial Interface.
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
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