Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 519

LPC Interface Bridge Registers (D31:F0)
13.8.3.2 PM1_EN—Power Management 1 Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
Bit
15
14
13:11
10
9
8
7:6
5
4:1
0
Datasheet
PMBASE + 02h
Attribute:
0000h
No
Bits 0 7: Core,
–
Bits 8 9, 11 15: Resume,
– –
Bit 10: RTC
Reserved
PCI Express* Wake Disable(PCIEXPWAK_DIS) — R/W. Modification of this bit has
no impact on the value of the PCIEXP_WAKE_STS bit.
0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake
the system.
1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from
waking the system.
Reserved
RTC Event Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC event
to wake after a power failure. In addition to being cleared by RTCRST# assertion, the
PCH also clears this bit due to a Power Button Override event, Intel ME Initiated Power
Button Override, Intel ME Initiated Host Reset with Power down, SMBus unconditional
power down, processor thermal trip event, or due to an internal thermal sensor
catastrophic condition.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit
10) goes active.
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit
goes active.
Reserved.
Power Button Enable (PWRBTN_EN) — R/W. This bit is used to enable the setting
of the PWRBTN_STS bit to generate a power management event (SMI#, SCI).
PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by
the assertion of the power button. The Power Button is always enabled as a Wake
event.
0 = Disable.
1 = Enable.
Reserved.
Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit
(PMBASE + 00h, bit 5) are set, an SCI is raised.
0 = Disable.
1 = Enable SCI on GBL_STS going active.
Reserved.
Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction with
the SCI_EN bit (PMBASE + 04h, bit 0) as described below:
TMROF_EN SCI_EN
0 X
1 0
1 1
R/W
Size:
Usage:
Description
Effect when TMROF_STS is set
No SMI# or SCI
SMI#
SCI
16-bit
ACPI or Legacy
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