Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 5

5.8.4.3
5.8.4.4
5.8.4.5
5.8.4.6
5.8.4.7
5.8.4.8
5.8.4.9
5.8.4.10 Automatic End of Interrupt Mode .............................................. 148
5.8.5 Masking Interrupts ............................................................................... 149
5.8.5.1
5.8.5.2
5.8.6 Steering PCI Interrupts ......................................................................... 149
5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 150
5.9.1 Interrupt Handling................................................................................ 150
5.9.2 Interrupt Mapping ................................................................................ 150
5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 151
5.9.4 IOxAPIC Address Remapping ................................................................. 151
5.9.5 External Interrupt Controller Support ...................................................... 151
5.10 Serial Interrupt (D31:F0) ................................................................................. 152
5.10.1 Start Frame......................................................................................... 152
5.10.2 Data Frames........................................................................................ 153
5.10.3 Stop Frame ......................................................................................... 153
5.10.4 Specific Interrupts Not Supported Using SERIRQ ...................................... 153
5.10.5 Data Frame Format .............................................................................. 154
5.11 Real Time Clock (D31:F0)................................................................................. 155
5.11.1 Update Cycles...................................................................................... 155
5.11.2 Interrupts ........................................................................................... 156
5.11.3 Lockable RAM Ranges ........................................................................... 156
5.11.4 Century Rollover .................................................................................. 156
5.11.5 Clearing Battery-Backed RTC RAM .......................................................... 156
5.12 Processor Interface (D31:F0) ............................................................................ 158
5.12.1 Processor Interface Signals and VLW Messages ........................................ 158
5.12.1.1 A20M# (Mask A20) / A20GATE ................................................. 158
5.12.1.2 INIT (Initialization) ................................................................. 159
5.12.1.3 FERR# (Numeric Coprocessor Error) .......................................... 159
5.12.1.4 NMI (Non-Maskable Interrupt) .................................................. 160
5.12.1.5 Processor Power Good (PROCPWRGD) ....................................... 160
5.12.2 Dual-Processor Issues........................................................................... 160
5.12.2.1 Usage Differences ................................................................... 160
5.12.3 Virtual Legacy Wire (VLW) Messages....................................................... 160
5.13 Power Management ......................................................................................... 161
5.13.1 Features ............................................................................................. 161
5.13.2 PCH and System Power States ............................................................... 161
5.13.3 System Power Planes ............................................................................ 163
5.13.4 SMI#/SCI Generation ........................................................................... 163
5.13.4.1 PCI Express* SCI.................................................................... 165
5.13.4.2 PCI Express* Hot-Plug............................................................. 165
5.13.5 C-States ............................................................................................. 166
5.13.6 Dynamic PCI Clock Control (Mobile Only)................................................. 166
5.13.6.1 Conditions for Checking the PCI Clock........................................ 166
5.13.6.2 Conditions for Maintaining the PCI Clock .................................... 166
5.13.6.3 Conditions for Stopping the PCI Clock ........................................ 166
5.13.6.4 Conditions for Re-Starting the PCI Clock .................................... 167
5.13.6.5 LPC Devices and CLKRUN#....................................................... 167
5.13.7 Sleep States ........................................................................................ 167
5.13.7.1 Sleep State Overview .............................................................. 167
5.13.7.2 Initiating Sleep State............................................................... 167
5.13.7.3 Exiting Sleep States ................................................................ 168
5.13.7.4 PCI Express* WAKE# Signal and PME Event Message .................. 170
5.13.7.5 Sx-G3-Sx, Handling Power Failures ........................................... 170
5.13.7.6 Deep S4/S5 ........................................................................... 171
5.13.8 Event Input Signals and Their Usage....................................................... 172
5.13.8.1 PWRBTN# (Power Button)........................................................ 172
5.13.8.2 RI# (Ring Indicator)................................................................ 174
5.13.8.3 PME# (PCI Power Management Event)....................................... 174
5.13.8.4 SYS_RESET# Signal ................................................................ 174
5.13.8.5 THRMTRIP# Signal.................................................................. 174
Datasheet
Automatic Rotation Mode (Equal Priority Devices)........................ 147
Specific Rotation Mode (Specific Priority).................................... 147
Poll Mode............................................................................... 147
Cascade Mode ........................................................................ 148
Edge and Level Triggered Mode ................................................ 148
End of Interrupt (EOI) Operations ............................................. 148
Normal End of Interrupt........................................................... 148
Masking on an Individual Interrupt Request................................ 149
Special Mask Mode.................................................................. 149
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