Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 395

Chipset Configuration Registers
10.1.50 CIR8—Chipset Initialization Register 8
Offset Address: 3324–3327h
Default Value:
Bit
31:0
10.1.51 DEEP_S4_POL—Deep S4 Power Policies
Offset Address: 332C–332Fh
Default Value:
This register is in the RTC power well and is reset by RTCRST# assertion.
Bit
31:2
1
0
10.1.52 DEEP_S5_POL—Deep S5 Power Policies
Offset Address: 3330–3333h
Default Value:
This register is in the RTC power well and is reset by RTCRST# assertion.
Bit
31:16
15
14
13:0
10.1.53 CIR10—Chipset Initialization Register 10
Offset Address: 3340–3343h
Default Value:
Bit
31:20
19:0
Datasheet
00000000h
CIR8 Field 1 — R/W. BIOS must program this field to 04000000h.
00000000h
Reserved.
Deep S4 Enable in DC Mode (DPS4_EN_DC) — R/W. A '1' in this bit enables the
platform to enter Deep S4 while operating on DC power (based on the AC_PRESENT
pin value).
Deep S4 Enable in AC Mode (DPS4_EN_AC) — R/W. A '1' in this bit enables the
platform to enter Deep S4 while operating on AC power (based on the AC_PRESENT
pin value). Required to be programmed to 0 on mobile.
00000000h
Reserved.
Deep S5 Enable in DC Mode (DPS5_EN_DC) — R/W. A '1' in this bit enables the
platform to enter Deep S5 while operating on DC power (based on the AC_PRESENT
pin value).
Deep S5 Enable in AC Mode (DPS5_EN_AC) — R/W. A '1' in this bit enables the
platform to enter Deep S5 while operating on AC power (based on the AC_PRESENT
pin value). Required to be programmed to 0 on mobile.
Reserved.
00000000h
Reserved
CIR10 Field 1 — R/W. BIOS must program this field to FFFFFh.
Attribute: R/W
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Description
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