Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 450

Bit
11
10:9
8
7
6
5
4
3
2:0
13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)
Offset Address: 08h
Default Value:
Bit
Revision ID (RID) — R/WO. See the Intel
7:0
the value of the RID Register..
13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)
Offset Address: 09h
Default Value:
Bit
7:0 Programming Interface — RO.
450
Signaled Target Abort (STA) — R/WC.
0 = Target abort Not generated on the backbone.
1 = LPC bridge generated a completion packet with target abort status on the
backbone.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
• LPC bridge receives a completion packet from the backbone from a previous
request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set.
Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal
backbone.
Reserved.
66 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on the internal
backbone.
Capabilities List (CLIST) — RO. Capability list exists on the LPC bridge.
Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.
Reserved.
See bit description
00h
LPC Interface Bridge Registers (D31:F0)
Description
Attribute: R/WO
Size: 8 bits
Description
®
6 Series Chipset Specification Update for
Attribute: RO
Size: 8 bits
Description
Datasheet