Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 558

14.1.12 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2)
Address Offset: 14h
Default Value:
.
Bit
31:16 Reserved
Base Address — R/W. This field provides the base address of the I/O space (4
15:2
consecutive I/O locations).
1 Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller's Control Block.
14.1.13 SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F2)
Address Offset: 18h
Default Value:
Bit
31:16 Reserved
Base Address — R/W. This field provides the base address of the I/O space (8
15:3
consecutive I/O locations).
2:1 Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 8-byte I/O space is used in native mode for the Secondary Controller's Command
Block.
14.1.14 SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F2)
Address Offset: 1Ch
Default Value:
Bit
31:16 Reserved
Base Address — R/W. This field provides the base address of the I/O space (4
15:2
consecutive I/O locations).
1 Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller's Control Block.
558
17h
–
00000001h
1Bh
–
00000001h
1Fh
–
00000001h
SATA Controller Registers (D31:F2)
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Datasheet