Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 491

LPC Interface Bridge Registers (D31:F0)
13.4.10 ELCR1—Master Controller Edge/Level Triggered Register
Offset Address: 4D0h
Default Value:
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade
channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),
cannot be put into level mode.
Bit
IRQ7 ECL — R/W.
7
0 = Edge
1 = Level
IRQ6 ECL — R/W.
6
0 = Edge
1 = Level.
IRQ5 ECL — R/W.
5
0 = Edge
1 = Level
IRQ4 ECL — R/W.
4
0 = Edge
1 = Level
IRQ3 ECL — R/W.
3
0 = Edge
1 = Level
2:0 Reserved. Must be 0.
Datasheet
00h
Attribute: R/W
Size: 8 bits
Description
491