Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 490

13.4.9 OCW3—Operational Control Word 3 Register
Offset Address: Master Controller
Default Value:
Bit
7 Reserved. Must be 0.
Special Mask Mode (SMM) — WO.
1 = The Special Mask Mode can be used by an interrupt service routine to dynamically
6
Enable Special Mask Mode (ESMM) — WO.
5
0 = Disable. The SMM bit becomes a "don't care".
1 = Enable the SMM bit to set or reset the Special Mask Mode.
4:3 OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01
Poll Mode Command — WO.
0 = Disable. Poll Command is not issued.
2
1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt
Register Read Command — WO. These bits provide control for reading the In-Service
Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not
affect the register read selection. When bit 1=1, bit 0 selects the register status
returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR
will be read. Following ICW initialization, the default OCW3 port address read will be
"read IRR". To retain the current selection (read ISR or read IRR), always write a 0 to
bit 1 when programming this register. The selected register can be read repeatedly
1:0
without reprogramming OCW3. To select a new status register, OCW3 must be
reprogrammed prior to attempting the read.
00 = No Action
01 = No Action
10 = Read IRQ Register
11 = Read IS Register
490
Slave Controller
–
Bit[6,0]=0, Bit[7,4:2]=undefined,
Bit[5,1]=1
alter the system priority structure while the routine is executing, through selective
enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be
set for this bit to have any meaning.
acknowledge cycle. An encoded byte is driven onto the data bus, representing the
highest priority level requesting service.
LPC Interface Bridge Registers (D31:F0)
020h Attribute:
–
0A0h Size:
Description
WO
8 bits
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