Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 660

16.1.35 FLR_CTRL—Function Level Reset Control Register
(USB EHCI—D29:F0, D26:F0)
Address Offset:
Default Value:
Function Level Reset: No
Bit
7:1 Reserved
Initiate FLR — R/W. This bit is used to initiate FLR transition. A write of 1 initiates FLR
0 transition. Since hardware must not respond to any cycles until FLR completion, the
value read by software from this bit is always 0.
16.1.36 FLR_STS—Function Level Reset Status Register
(USB EHCI—D29:F0, D26:F0)
Address Offset:
Default Value:
Function Level Reset: No
Bit
7:1 Reserved
Transactions Pending (TXP) — RO.
0
0 = Completions for all non-posted requests have been received.
1 = Controller has issued non-posted requests which have no bee completed.
660
9Ch
00h
9Dh
00h
EHCI Controller Registers (D29:F0, D26:F0)
Attribute: R/W
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Datasheet