Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 547

LPC Interface Bridge Registers (D31:F0)
13.10.12 GP_IO_SEL2—GPIO Input/Output Select 2 Register
Offset Address: GPIOBASE +34h
Default Value:
Lockable:
Bit
31:0
13.10.13 GP_LVL2—GPIO Level for Input or Output 2 Register
Offset Address: GPIOBASE +38h
Default Value:
Lockable:
Bit
31:0
Datasheet
1F57FFF4h
Yes
GP_IO_SEL2[63:32] — R/W.
0 = GPIO signal is programmed as an output.
1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is
programmed as an input.
This register corresponds to GPIO[63:32]. Bit 0 corresponds to GPIO32.
A4AA0007h
Yes
GP_LVL[63:32] — R/W. These registers are implemented as dual read/write with
dedicated storage each. Write value will be stored in the write register, while read is
coming from the read register which will always reflect the value of the pin. If GPIO[n]
is programmed to be an output (using the corresponding bit in the GP_IO_SEL
register), then the corresponding GP_LVL[n] write register value will drive a high or low
value on the output pin.
1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
NOTE: This register corresponds to GPIO[63:32]. Bit 0 corresponds to GPIO32.
Attribute: R/W
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
547