Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 622

15.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F5)
Address Offset: 0Dh
Default Value:
Bit
7:0
15.1.10 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F5)
Address Offset: 10h
Default Value:
.
Bit
31:16 Reserved
Base Address — R/W. This field provides the base address of the I/O space (8
15:3
consecutive I/O locations).
2:1 Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller's Command Block.
15.1.11 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F5)
Address Offset: 14h
Default Value:
.
Bit
31:16 Reserved
Base Address — R/W. This field provides the base address of the I/O space (4
15:2
consecutive I/O locations).
1 Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller's Command Block.
622
00h
Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated
as a PCI device, so it does not need a Master Latency Timer.
13h
–
00000001h
17h
–
00000001h
SATA Controller Registers (D31:F5)
Attribute: RO
Size: 8 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: R/W, RO
Size: 32 bits
Description
Datasheet