Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 709

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Integrated Intel High Definition Audio Controller Registers
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Table 17-2. Intel High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel
HDBAR +
Offset
124h–127h
128h–12Bh
12Ch–12Dh
12Eh–12Fh
130h–131h
132h–133h
138h–13Bh
13Ch–13Fh
140h–142h
143h
144h–147h
148h–14Bh
14Ch–14Dh
14Eh–14Fh
150h–151h
152h–153h
158h–15Bh
15Ch–15Fh
160h–162h
163h
164h–167h
168h–16Bh
16Ch–16Dh
16Eh–16Fh
170h–171h
172h–173h
178h–17Bh
17Ch–17Fh
Datasheet
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High Definition Audio D27:F0) (Sheet 4 of 4)
Mnemonic
OSD1LPIB OSD1 Link Position in Buffer
OSD1CBL OSD1 Cyclic Buffer Length
OSD1LVI OSD1 Last Valid Index
OSD1FIFOW OSD1 FIFO Watermark
OSD1FIFOS OSD1 FIFO Size
OSD1FMT OSD1 Format
OSD1 Buffer Descriptor List Pointer –
OSD1BDPL
Lower Base Address
OSD1 Buffer Description List Pointer –
OSD1BDPU
Upper Base Address
Output Stream Descriptor 2 (OSD2)
OSD2CTL
Control
OSD2STS OSD2 Status
OSD2LPIB OSD2 Link Position in Buffer
OSD2CBL OSD2 Cyclic Buffer Length
OSD2LVI OSD2 Last Valid Index
OSD2FIFOW OSD2 FIFO Watermark
OSD2FIFOS OSD2 FIFO Size
OSD2FMT OSD2 Format
OSD2 Buffer Descriptor List Pointer –
OSD2BDPL
Lower Base Address
OSD2 Buffer Description List Pointer –
OSD2BDPU
Upper Base Address
Output Stream Descriptor 3 (OSD3)
OSD3CTL
Control
OSD3STS OSD3 Status
OSD3LPIB OSD3 Link Position in Buffer
OSD3CBL OSD3 Cyclic Buffer Length
OSD3LVI OSD3 Last Valid Index
OSD3FIFOW OSD3 FIFO Watermark
OSD3FIFOS OSD3 FIFO Size
OSD3FMT OSD3 Format
OSD3 Buffer Descriptor List Pointer –
OSD3BDPL
Lower Base Address
OSD3 Buffer Description List Pointer –
OSD3BDPU
Upper Base Address
Register Name Default Access
00000000h RO
00000000h R/W
0000h R/W
0004h R/W
0000h R/W
0000h R/W
00000000h R/W, RO
00000000h R/W
040000h R/W, RO
00h R/WC, RO
00000000h RO
00000000h R/W
0000h R/W
0004h R/W
0000h R/W
0000h R/W
00000000h R/W, RO
00000000h R/W
040000h R/W, RO
00h R/WC, RO
00000000h RO
00000000h R/W
0000h R/W
0004h R/W
0000h R/W
0000h R/W
00000000h R/W, RO
00000000h R/W
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