Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 908

23.6.11 IDECLIR—IDE Cylinder Low In Register Register
(IDER—D22:F2)
Address Offset: 04h
Default Value:
This register implements the Cylinder Low register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDECLIR, IDECLOR0, IDECLOR1) are updated with the written
value.
Host read to this register address reads the IDE Cylinder Low Out Register IDECLOR0 if
DEV=0 or IDECLOR1 if DEV=1.
Bit
7:0
23.6.12 IDCLOR1—IDE Cylinder Low Out Register Device 1
Register (IDER—D22:F2)
Address Offset: 04h
Default Value:
This register is read by the Host if DEV = 1. ME-Firmware writes to this register at the
end of a command of the selected device. When the host writes to the IDE Cylinder Low
In Register (IDECLIR), this register is updated with that value.
Bit
7:0
908
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
00h
IDE Cylinder Low Data (IDECLD) — R/W. Cylinder Low register of the command
block of the IDE function.
00h
IDE Cylinder Low Out DEV 1. (IDECLO1) — R/W. Cylinder Low Out Register for
Slave Device.
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 8 bits
Description
Datasheet