Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 88

Table 2-27. Functional Strap Definitions (Sheet 2 of 5)
Signal
GNT1#/GPIO51
88
When
Usage
Sampled
Boot BIOS Strap
Rising edge of
bit 1
PWROK
BBS1
Comment
This Signal has a weak internal pull-up.
Note: the internal pull-up is disabled after
PLTRST# deasserts.
This field determines the destination of accesses
to the BIOS memory range. Also controllable
using Boot BIOS Destination bit (Chipset Config
Registers: Offset 3410h:Bit 11). This strap is
used in conjunction with Boot BIOS Destination
Selection 0 strap.
Boot BIOS
Bit11 Bit 10
Destination
0 1 Reserved
1 0
1 1
0 0
NOTES:
1. If option 00 (LPC) is selected, BIOS may
still be placed on LPC, but all platforms
are required to have SPI flash connected
directly to the PCH's SPI bus with a valid
descriptor in order to boot.
2. Booting to PCI is intended for debut/
testing only. Boot BIOS Destination
Select to LPC/PCI by functional strap or
using Boot BIOS Destination Bit will not
affect SPI accesses initiated by Intel
or Integrated GbE LAN.
3. PCI Boot BIOS destination is not
supported on Mobile
Signal Description
PCI
SPI
LPC
®
ME
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