Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 691

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Integrated Intel High Definition Audio Controller Registers
17.1.1.17 INTLN—Interrupt Line Register
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(Intel
Address Offset: 3Ch
Default Value:
Bit
7:0
17.1.1.18 INTPN—Interrupt Pin Register
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(Intel
Address Offset: 3Dh
Default Value:
Bit
7:4 Reserved.
Interrupt Pin — RO. This reflects the value of D27IP.ZIP (Chipset Config
3:0
Registers:Offset 3110h:bits 3:0).
17.1.1.19 HDCTL—Intel
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(Intel
Address Offset: 40h
Default Value:
Bit
7:1 Reserved.
Intel
0
This bit is hardwired to 1 (High Definition Audio mode).
Datasheet
High Definition Audio Controller—D27:F0)
00h
Interrupt Line (INT_LN) — R/W. This data is not used by the PCH. It is used to
communicate to software the interrupt line that the interrupt pin is connected to.
High Definition Audio Controller—D27:F0)
See Description
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High Definition Audio Control Register
High Definition Audio Controller—D27:F0)
01h
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High Definition Signal Mode — RO.
Attribute: R/W
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
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