Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 606

Bit
Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and
23 PxIS.IPMS are set, the PCH will generate an interrupt.
NOTE: FIS based Port Multipliers only supported on SATA ports 4 and 5 by PCH
PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and
22
PxIS.PRCS is set, the PCH shall generate an interrupt.
21:8 Reserved
Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the PCH will
generate an interrupt.
7
For systems that do not support an mechanical presence switch, this bit shall be a read-
only 0.
Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS
6
are set, the PCH will generate an interrupt.
Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and
5
PxS.DPS are set, the PCH will generate an interrupt.
Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an
4
unknown FIS is received, the PCH will generate this interrupt.
Set Device Bits FIS Interrupt Enable (SDBE) — R/W. When set, and GHC.IE and
3
PxS.SDBS are set, the PCH will generate an interrupt.
DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS
2
are set, the PCH will generate an interrupt.
PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS
1
are set, the PCH will generate an interrupt.
Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and
0
GHC.IE and PxS.DHRS are set, the PCH will generate an interrupt.
606
SATA Controller Registers (D31:F2)
Description
Datasheet