Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 667

EHCI Controller Registers (D29:F0, D26:F0)
Bit
Run/Stop (RS) — R/W.
0 = Stop (default)
1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule.
Software should not write a 1 to this field unless the host controller is in the Halted
state (that is, HCHalted in the USBSTS register is a 1). The Halted bit is cleared
immediately when the Run bit is set.
The following table explains how the different combinations of Run and Halted should
0
be interpreted:
Memory read cycles initiated by the EHC that receive any status other than Successful
will result in this bit being cleared.
NOTE: The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed.
Datasheet
The Host controller continues execution as long as this bit is set. When this bit is
set to 0, the Host controller completes the current transaction on the USB and then
halts. The HCHalted bit in the USB2.0_STS register indicates when the Host
controller has finished the transaction and has entered the stopped state.
Run/Stop Halted Interpretation
0b 0b In the process of halting
0b 1b Halted
1b 0b Running
1b 1b Invalid – the HCHalted bit clears immediately
Description
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