Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 773

PCI Express* Configuration Registers
19.1.27 DSTS—Device Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 4Ah–4Bh
Default Value:
Bit
15:6
5
4
3
2
1
0
Datasheet
0010h
Reserved
Transactions Pending (TDP) — RO. This bit has no meaning for the root port since
only one transaction may be pending to the PCH, so a read of this bit cannot occur until
it has already returned to 0.
AUX Power Detected (APD) — RO. The root port contains AUX power for wakeup.
Unsupported Request Detected (URD) — R/WC. Indicates an unsupported request
was detected.
Fatal Error Detected (FED) — R/WC. Indicates a fatal error was detected.
0 = Fatal has not occurred.
1 = A fatal error occurred from a data link protocol error, link training error, buffer
overflow, or malformed TLP.
Non-Fatal Error Detected (NFED) — R/WC. Indicates a non-fatal error was detected.
0 = Non-fatal has not occurred.
1 = A non-fatal error occurred from a poisoned TLP, unexpected completions,
unsupported requests, completer abort, or completer timeout.
Correctable Error Detected (CED) — R/WC. Indicates a correctable error was
detected.
0 = Correctable has not occurred.
1 = The port received an internal correctable error from receiver errors / framing
errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout.
Attribute: R/WC, RO
Size: 16 bits
Description
773