Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 600

Table 14-5. Port [5:0] DMA Register Address Map (Sheet 2 of 3)
ABAR +
Offset
200h–27Fh
200h–203h
204h–207h
208h–20Bh
20Ch–20Fh
210h–213h
214h–217h
218h–21Bh
21Ch–21Fh
220h–223h
224h–227h
228h–22Bh
22Ch–22Fh
230h–233h
234h–237h
238h–23Bh
23Ch–27Fh
280h–2FFh
280h–283h
284h–287h
288h–28Bh
28Ch–28Fh
290h–293h
294h–297h
298h–29Bh
29Ch–29Fh
2A0h–2A3h
2A4h–2A7h
2A8h–2ABh
2ACh–2AFh
2B0h–2B3h
2B4h–2B7h
2B8h–2BBh
2BCh–2FFh
300h–303h
304h–307h
600
Mnemonic
Registers may be Reserved depending on if port is available in
—
the given SKU. See
P2CLB Port 2 Command List Base Address
P2CLBU Port 2 Command List Base Address Upper 32-Bits
P2FB Port 2 FIS Base Address
P2FBU Port 2 FIS Base Address Upper 32-Bits
P2IS Port 2 Interrupt Status
P2IE Port 2 Interrupt Enable
P2CMD Port 2 Command
— Reserved
P2TFD Port 2 Task File Data
P2SIG Port 2 Signature
P2SSTS Port 2 Serial ATA Status
P2SCTL Port 2 Serial ATA Control
P2SERR Port 2 Serial ATA Error
P2SACT Port 2 Serial ATA Active
P2CI Port 2 Command Issue
— Reserved
Registers may be Reserved depending on if port is available in
—
the given SKU. See
P3CLB Port 3 Command List Base Address
P3CLBU Port 3 Command List Base Address Upper 32-Bits
P3FB Port 3 FIS Base Address
P3FBU Port 3 FIS Base Address Upper 32-Bits
P3IS Port 3 Interrupt Status
P3IE Port 3 Interrupt Enable
P3CMD Port 3 Command
— Reserved
P3TFD Port 3 Task File Data
P3SIG Port 3 Signature
P3SSTS Port 3 Serial ATA Status
P3SCTL Port 3 Serial ATA Control
P3SERR Port 3 Serial ATA Error
P3SACT Port 3 Serial ATA Active
P3CI Port 3 Command Issue
— Reserved
P4CLB Port 4 Command List Base Address
P4CLBU Port 4 Command List Base Address Upper 32-Bits
SATA Controller Registers (D31:F2)
Register
Section 1.3 for details if port is available.
Section 1.3 for details if port is available.
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