Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 550

13.10.18 GP_RST_SEL2 — GPIO Reset Select
Offset Address: GPIOBASE +64h
Default Value:
Lockable:
Bit
GP_RST_SEL[63:56] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK deassertion, CF9h reset (06h
31:24
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
23:16 Reserved
GP_RST_SEL[47:40] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK deassertion, CF9h reset (06h
15:8
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
13.10.19 GP_RST_SEL3 — GPIO Reset Select
Offset Address: GPIOBASE +68h
Default Value:
Lockable:
Bit
31:12 Reserved
GP_RST_SEL[75:72] — R/W.
0 = Corresponding GPIO registers will be reset by PWROK deassertion, CF9h reset (06h
11:8
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
550
00000000h
Yes
or 0Eh), or SYS_RESET# assertion.
or 0Eh), or SYS_RESET# assertion.
00000000h
Yes
or 0Eh), or SYS_RESET# assertion.
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
Attribute: R/W
Size: 32-bit
Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Description
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