Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 488

13.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register
Offset Address: A1h
Default Value:
Bit
7:3 0 = These bits must be programmed to 0.
Slave Identification Code — WO. These bits are compared against the slave
identification code broadcast by the master controller from the trailing edge of the first
internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits
2:0
must be programmed to 02h to match the code broadcast by the master controller.
When 02h is broadcast by the master controller during the INTA# sequence, the slave
controller assumes responsibility for broadcasting the interrupt vector.
13.4.6 ICW4—Initialization Command Word 4 Register
Offset Address: Master Controller
Default Value:
Bit
7:5 0 = These bits must be programmed to 0.
Special Fully Nested Mode (SFNM) — WO.
4
0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
Buffered Mode (BUF) — WO.
3
0 = Must be programmed to 0 for the PCH. This is non-buffered mode.
Master/Slave in Buffered Mode — WO. Not used.
2
0 = Should always be programmed to 0.
Automatic End of Interrupt (AEOI) — WO.
1
0 = This bit should normally be programmed to 0. This is the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is programmed.
Microprocessor Mode — WO.
0 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel
488
All bits undefined
Slave Controller
–
01h
Architecture-based system.
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Description
021h Attribute:WO
–
0A1h Size: 8 bits
Description
WO
8 bits
Datasheet