Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 250

5.24.4.4.1 Single Input, Dual Output Fast Read
The PCH now supports the functionality of a single input, dual output fast read. Opcode
and address phase are shifted in serially to the serial flash SI (Serial In) pin. Data is
read out after 8 clocks (dummy bits or wait states) from the both the SI and SO pin
effectively doubling the through put of each fast read output. In order to enable this
functionality, both Single Input Dual Output Fast Read Supported and Fast Read
supported must be enabled
5.24.4.4.2 Serial Flash Discoverable Parameters (SFDP)
As the number of features keeps growing in the serial flash, the need for correct,
accurate configuration increases. A new method of determining configuration
information is Serial Flash Discoverable Parameters (SFDP). Information such as VSCC
values and flash attributes can be read directly from the flash parts. The discoverable
parameter read opcode behaves like a fast read command. The opcode is 5Ah and the
address cycle is 24 bits long. After the opcode 5Ah and address are clocked in, there
will then be eight clocks (8 wait states) before valid data is clocked out. SFDP is a
capability of the flash part, please confirm with target flash vendor to see if it is
supported.
In order for BIOS to take advantage of the 5Ah opcode it needs to be programmed in
the Software sequencing registers.
5.24.4.4.3 JEDEC ID
Since each serial flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.
5.24.5 Multiple Page Write Usage Model
The system BIOS and Intel Management Engine firmware usage models require that
the serial flash device support multiple writes to a page (minimum of 512 writes)
without requiring a preceding erase command. BIOS commonly uses capabilities such
as counters that are used for error logging and system boot progress logging. These
counters are typically implemented by using byte-writes to 'increment' the bits within a
page that have been designated as the counter. The Intel ME firmware usage model
requires the capability for multiple data updates within any given page. These data
updates occur using byte-writes without executing a preceding erase to the given page.
Both the BIOS and Intel
sequential and non-sequential data writes.
Note: This usage model requirement is based on any given bit only being written once from a
'1' to a '0'without requiring the preceding erase. An erase would be required to change
bits back to the 1 state.
5.24.5.1 Soft Flash Protection
There are two types of flash protection that are not defined in the flash descriptor
supported by PCH:
1. BIOS Range Write Protection
2. SMI#-Based Global Write Protection
250
®
ME firmware multiple page write usage models apply to
Functional Description
Datasheet