Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 408

10.1.77 DISPBDF—Display Bus, Device and Function Initialization
Offset Address: 3424–3425h
Default Value:
Bit
15:8
7:3
2:0
10.1.78 FD2—Function Disable 2
Offset Address: 3428–342Bh
Default Value:
Bit
31:5
4
3
2
1
0
408
0010h
Display Bus Number (DBN) — R/W. The bus number of the Display in the
processor. BIOS should always program these bits as 0.
Display Device Number (DDN) — R/W. The device number of the Display in the
processor. BIOS should always program these bits as 2.
Display Function Number (DFN) — R/W. The function number of the Display in the
processor. BIOS should always program these bits as 0.
00000000h
Reserved
KT Disable (KTD) —R/W. Default is 0.
0 = Keyboard Text controller (D22:F3) is enabled.
1 = Keyboard Text controller (D22:F3) is Disabled
IDE-R Disable (IRERD) —R/W. Default is 0.
0 = IDE Redirect controller (D22:F2) is Enabled.
1 = IDE Redirect controller (D22:F2) is Disabled.
®
Intel MEI #2 Disable (MEI2D) —R/W. Default is 0.
0 = Intel MEI controller #2 (D22:F1) is enabled.
1 = Intel MEI controller #2 (D22:F1) is disabled.
Intel MEI #1 Disable (MEI1D) —R/W. Default is 0.
0 = Intel MEI controller #1 (D22:F0) is enabled.
1 = Intel MEI controller #1 (D22:F0) is disabled.
Display BDF Enable (DBDFEN) —R/W.
Chipset Configuration Registers
Attribute: R/W
Size: 16-bit
Description
Attribute: R/W
Size: 32-bit
Description
Datasheet