Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 720

17.1.2.23 RIRBLBASE—RIRB Lower Base Address Register
®
(Intel
Memory Address:HDBAR + 50h
Default Value:
Bit
CORB Lower Base Address — R/W. Lower address of the Response Input Ring Buffer,
allowing the RIRB base address to be assigned on any 128-B boundary. This register
31:7
field must not be written when the DMA engine is running or the DMA transfer may be
corrupted.
RIRB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the RIRB to
6:0
be allocated with 128-B granularity to allow for cache line fetch optimizations.
17.1.2.24 RIRBUBASE—RIRB Upper Base Address Register
®
(Intel
Memory Address:HDBAR + 54h
Default Value:
Bit
RIRB Upper Base Address — R/W. Upper 32 bits of the address of the Response
31:0 Input Ring Buffer. This register field must not be written when the DMA engine is
running or the DMA transfer may be corrupted.
17.1.2.25 RIRBWP—RIRB Write Pointer Register
®
(Intel
Memory Address:HDBAR + 58h
Default Value:
Bit
RIRB Write Pointer Reset — R/W. Software writes a 1 to this bit to reset the RIRB
Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write
15
Pointer or else DMA transfer may be corrupted.
This bit is always read as 0.
14:8 Reserved.
RIRB Write Pointer (RIRBWP) — RO. Indicates the last valid RIRB entry written by
the DMA controller. Software reads this field to determine how many responses it can
read from the RIRB. The value read indicates the RIRB Write Pointer offset in 2 DWord
7:0
RIRB entry units (since each RIRB entry is 2 DWords long). Supports up to 256 RIRB
entries (256 x 8 B = 2 KB). This register field may be written when the DMA engine is
running.
720
High Definition Audio Controller—D27:F0)
00000000h
High Definition Audio Controller—D27:F0)
00000000h
High Definition Audio Controller—D27:F0)
0000h
®
Integrated Intel High Definition Audio Controller Registers
Attribute:
Size:
Description
Attribute:
Size:
Description
Attribute:
Size:
Description
R/W, RO
32 bits
R/W
32 bits
R/W, RO
16 bits
Datasheet