Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 743

SMBus Controller Registers (D31:F3)
18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1
(SMBus—D31:F3)
Address Offset: 14h–17h
Default Value:
Bit
31:0
18.1.11 SMB_BASE—SMBus Base Address Register
(SMBus—D31:F3)
Address Offset: 20
Default Value:
Bit
31:16 Reserved — RO
Base Address — R/W. This field provides the 32-byte system I/O base address for the
15:5
PCH's SMB logic.
4:1 Reserved — RO
0 IO Space Indicator — RO. Hardwired to 1 indicating that the SMB logic is I/O mapped.
18.1.12 SVID—Subsystem Vendor Identification Register
(SMBus—D31:F2/F4)
Address Offset: 2Ch
Default Value:
Lockable:
Bit
Subsystem Vendor ID (SVID) — RO. The SVID register, in combination with the
Subsystem ID (SID) register, enables the operating system (OS) to distinguish
subsystems from each other. The value returned by reads to this register is the same as
15:0
that which was written by BIOS into the IDE SVID register.
NOTE: Software can write to this register only once per core well reset. Writes should
Datasheet
00000000h
Base Address — R/W. Provides bits 63:32 system memory base address for the PCH
SMB logic.
23h
–
00000001h
2Dh
–
0000h
No
be done as a single 16-bit cycle.
Attributes: R/W
Size: 32 bits
Description
Attribute: R/W, RO
Size: 32-bits
Description
Attribute: RO
Size: 16 bits
Power Well: Core
Description
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