Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 849

Hide thumbs Also See for 6 SERIES CHIPSET - DATASHEET 01-2011:
Table of Contents

Advertisement

Thermal Sensor Registers (D31:F6)
22.1.12
TBAR—Thermal Base
Address Offset: 10h
Default Value:
This BAR creates 4K bytes of memory space to signify the base address of Thermal
memory mapped configuration registers. This memory space is active when the
Command (CMD) register Memory Space Enable (MSE) bit is set and either
TBAR[31:12] or TBARH are programmed to a non-zero address. This BAR is owned by
the Operating System, and allows the OS to locate the Thermal registers in system
memory space.
Bit
31:12
11:4
3
2:1
0
22.1.13
TBARH—Thermal Base High DWord
Address Offset: 14h
Default Value:
This BAR extension holds the high 32 bits of the 64 bit TBAR. In conjunction with TBAR,
it creates 4 KB of memory space to signify the base address of Thermal memory
mapped configuration registers.
Bit
31:0
22.1.14
SVID—Subsystem Vendor ID
Address Offset: 2Ch
Default Value:
This register should be implemented for any function that could be instantiated more
than once in a given system. The SVID register, in combination with the Subsystem ID
register, enables the operating environment to distinguish one subsystem from the
other(s).
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SID to create one 32-bit write. This register is not
affected by D3
Bit
15:0
Datasheet
13h
00000004h
Thermal Base Address (TBA) — R/W. This field provides the base address for the
Thermal logic memory mapped configuration registers. 4 KB bytes are requested by
hardwiring bits 11:4 to 0s.
Reserved
Prefetchable (PREF) — RO. Indicates that this BAR is NOT pre-fetchable.
Address Range (ADDRNG) — RO. Indicates that this BAR can be located anywhere
in 64 bit address space.
Space Type (SPTYP) — RO. Indicates that this BAR is located in memory space.
17h
00000000h
Thermal Base Address High (TBAH) — R/W. TBAR bits 61:32.
2Dh
0000h
to D0 reset.
HOT
SVID (SVID) — R/WO. These R/WO bits have no PCH functionality.
Attribute:
R/W, RO
Size:
32 bits
Description
Attribute:
R/W, RO
Size:
32 bits
Description
Attribute:
R/WO
Size:
16 bits
Description
849

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

6 series

Table of Contents