Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 680

Bit
5
4
3:0
NOTES:
1. Software should do Read-Modify-Write operations to this register to preserve the contents
of bits not being modified. This include Reserved bits.
2. To preserve the usage of RESERVED bits in the future, software should always write the
same value read from the bit until it is defined. Reserved bits will always return 0 when
read.
680
GO_CNT — R/W.
0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default)
1 = Causes hardware to perform a read or write request.
NOTE: Writing a 1 to this bit when it is already set may result in undefined behavior.
WRITE_READ#_CNT — R/W. Software clears this bit to indicate that the current
request is a read. Software sets this bit to indicate that the current request is a write.
0 = Read (Default)
1 = Write
DATA_LEN_CNT — R/W. This field is used to indicate the size of the data to be
transferred.
default = 0h.
For write operations, this field is set by software to indicate to the hardware how
many bytes of data in Data Buffer are to be transferred to the console. A value of 0h
indicates that a zero-length packet should be sent. A value of 1–8 indicates 1–8 bytes
are to be transferred. Values 9–Fh are invalid and how hardware behaves if used is
undefined.
For read operations, this field is set by hardware to indicate to software how many
bytes in Data Buffer are valid in response to a read operation. A value of 0h indicates
that a zero length packet was returned and the state of Data Buffer is not defined. A
value of 1–8 indicates 1–8 bytes were received. Hardware is not allowed to return
values 9–Fh.
The transferring of data always starts with byte 0 in the data area and moves toward
byte 7 until the transfer size is reached.
EHCI Controller Registers (D29:F0, D26:F0)
Description
Datasheet