Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 658

Bit
3
2
1
0
16.1.30 ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F0, D26:F0)
Address Offset:
Default Value:
Function Level Reset: No
Bit
7:1
0
16.1.31 EHCIIR1—EHCI Initialization Register 1
(USB EHCI—D29:F0, D26:F0)
Address Offset:
Default Value:
Bit
31:5 Reserved
Pre-fetch Based Pause Enable — R/W.
4
0 = Pre-fetch Based Pause is disabled.
1 = Pre-fetch Based Pause is enabled.
3:0 Reserved
658
SMI on Periodic Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller
will issue an SMI.
SMI on CF Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will
issue an SMI.
SMI on HCHalted Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host
controller will issue an SMI.
SMI on HCReset Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller
will issue an SMI.
80h
00h
Reserved
WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally
read-only registers in the EHC function to be written by software. Registers that
may only be written when this mode is entered are noted in the summary tables
and detailed description as "Read/Write-Special". The registers fall into two
categories:
1. System-configured parameters
2. Status bits
84h
01h
EHCI Controller Registers (D29:F0, D26:F0)
Description
Attribute: R/W
Size: 8 bits
Description
Attribute: R/W
Size: 32 bits
Description
Datasheet