Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 590

14.4.1.1 CAP—Host Capabilities Register (D31:F2)
Address Offset: ABAR + 00h–03h
Default Value:
Function Level Reset:No
All bits in this register that are R/WO are reset only by PLTRST#.
Bit
31
30
29
28
27
26
25
24
23:20
19
590
FF22FFC2h (Desktop)
DE127F03h (Mobile)
Supports 64-bit Addressing (S64A) — RO. Indicates that the SATA controller can
access 64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the
PRD Base, and each PRD entry are read/write.
Supports Command Queue Acceleration (SCQA) — R/WO. When set to 1,
indicates that the SATA controller supports SATA command queuing using the DMA
Setup FIS. The PCH handles DMA Setup FISes natively, and can handle auto-
activate optimization through that FIS.
Supports SNotification Register (SSNTF) — RO. The PCH SATA Controller does not
support the SNotification register.
Supports Mechanical Presence Switch (SMPS) — R/WO. When set to 1,
indicates whether the SATA controller supports mechanical presence switches on its
ports for use in Hot Plug operations. This value is loaded by platform BIOS prior to
OS initialization.
If this bit is set, BIOS must also map the SATAGP pins to the SATA controller
through GPIO space.
Supports Staggered Spin-up (SSS) — R/WO. Indicates whether the SATA
controller supports staggered spin-up on its ports, for use in balancing power
spikes. This value is loaded by platform BIOS prior to OS initialization.
0 = Staggered spin-up not supported.
1 = Staggered spin-up supported.
Supports Aggressive Link Power Management (SALP) — R/WO.
0 = Software shall treat the PxCMD.ALPE and PxCMD.ASP bits as reserved.
1 = The SATA controller supports auto-generating link requests to the partial or
slumber states when there are no commands to process.
Supports Activity LED (SAL) — RO. Indicates that the SATA controller supports a
single output pin (SATALED#) which indicates activity.
Supports Command List Override (SCLO) — R/WO. When set to 1, indicates
that the Controller supports the PxCMD.CLO bit and its associated function. When
cleared to 0, the Controller is not capable of clearing the BSY and DRQ bits in the
Status register in order to issue a software reset if these bits are still set from a
previous operation.
Interface Speed Support (ISS) — R/WO. Indicates the maximum speed the
SATA controller can support on its ports.
1h = 1.5 Gb/s; 2h =3 Gb/s; 3h = 6 Gb/s
The default of this field is dependent upon the PCH SKU. If at least one PCH SATA
port supports 6 Gb/s, the default will be 3h. If no PCH SATA ports support 6 Gb/s,
then the default will be 2h and writes of 3h will be ignored by the PCH. See
Section 1.3 for details on 6 Gb/s port availability.
Supports Non-Zero DMA Offsets (SNZO) — RO. Reserved, as per the AHCI Revision
1.3 specification
SATA Controller Registers (D31:F2)
Attribute: R/WO, RO
Size: 32 bits
Description
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