Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 576

14.1.42 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)
Address Offset: E0h
Default Value:
Bits
31:16
15
14
13
12
576
E3h
–
00000000h
Reserved
Port 5 BIST FIS Initiate (P5BFI) — R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 5, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 5 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P5BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
Port 4 BIST FIS Initiate (P4BFI) — R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 4, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 4 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P4BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
Port 3 BIST FIS Initiate (P3BFI) — R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 3, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 3 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P3BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Port 2 BIST FIS Initiate (P2BFI) — R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 2, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 2 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISes or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P2BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
SATA Controller Registers (D31:F2)
Attribute: R/W, R/WC
Size: 32 bits
Description
Datasheet