Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 380

10.1.30 D31IP—Device 31 Interrupt Pin Register
Offset Address: 3100–3103h
Default Value:
Bit
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
380
03243200h
Reserved
Thermal Throttle Pin (TTIP) — R/W. Indicates which pin the Thermal Throttle
controller drives as its interrupt
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
SATA Pin 2 (SIP2) — R/W. Indicates which pin the SATA controller 2 drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Reserved
SMBus Pin (SMIP) — R/W. Indicates which pin the SMBus controller drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
SATA Pin (SIP) — R/W. Indicates which pin the SATA controller drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Reserved
LPC Bridge Pin (LIP) — RO. Currently, the LPC bridge does not generate an interrupt,
so this field is read-only and 0.
Chipset Configuration Registers
Attribute: R/W, RO
Size: 32-bit
Description
Datasheet