Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 333

Electrical Characteristics
1. VccSus supplies include VccSus3_3, V5REF_Sus, and VccSusHDA. Also includes DcpSus for
mobile platforms that power DcpSus externally.
2. This timing is a nominal value counted using RTC clock. If RTC clock isn't already stable at
the rising edge of RSMRST#, this timing could be shorter or longer than the specified
value.
3. Platforms not supporting Deep S4/S5 will typically have SLP_SUS# left as no connect.
Hence DPWROK high and RSMRST# deassertion to SUSCLK toggling would be
t202+t202a=100 ms minimum.
4. Platforms supporting Deep S4/S5 will have SLP_SUS# deassert prior to RSMRST#.
Platforms not supporting Deep S4/S5 will have RSMRST# deassert prior to SLP_SUS#.
5. Dependency on SLP_S4# and SLP_A# stretching
6. Dependency on SLP_S3# and SLP_A# stretching
7. It is required that the power rails associated with PCI/PCIe (typically the 3.3 V, 5 V, and
12 V core well rails) have been valid for 99 ms prior to PWROK assertion in order to comply
with the 100 ms PCI/PCIe 2.0 specification on PLTRST# deassertion. System designers
must ensure the requirement is met on the platforms.
8. Ensure PWROK is a solid logic '1' before proceeding with the boot sequence. Note: If
PWROK drops after t206 it will be considered a power failure.
9. Timing is dependant on whether 25 MHz crystal is stable by the time PWROK is high.
10. Requires SPI messaging to be completed.
11. The negative min timing implies that DRAMPWROK must either fall before SLP_S4# or
within 100 ns after it.
12. The VccDSW3_3 supplies must never be active while the VccRTC supply is inactive.
13. Vcc includes VccIO, VccCORE, Vcc3_3, VccADPLLA, VccADPLLB, VccADAC, V5REF,
V_PROC_IO, VccCLKDMI, VccDIFFCLKN, VccVRM, VccDFTERM, VccSSC, VccALVDS (mobile
only), VccTXLVDS (mobile only) and VccASW (if Intel
14. A Power rail is considered to be inactive when the rail is at its nominal voltage minus 5% or
less.
15. Board design may meet (t231 AND t232 AND t235) OR (t238).
16. V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must
power down after Vcc3_3, or before Vcc3_3 within 0.7 V. V5REF_Sus must be powered up
before VccSus3_3, or after VccSus3_3 within 0.7 V. Also, V5REF_Sus must power down
after VccSus3_3, or before VccSus3_3 within 0.7 V.
17. If RTC clock is not already stable at RSMRST# rising edge, this time may be longer.
18. RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.9 V
19. The 50 µs should be measured from Vih to Vil (2 V to 0.78 V).
20. This is an internal timing showing when the signals (SLP_S5#, SLP_S4#, SLP_S3#,
SUS_STAT#, PLTRST# and PCIRST#) are valid after VccSus rail is Active.
21. APWROK high to SPI Soft-Strap Read is an internal PCH timing. The timing cannot be
measured externally and included here for general power sequencing reference.
Datasheet
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ME only powered in S0).
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