Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 64

Table 2-8. Power Management Interface Signals (Sheet 2 of 4)
Name
DRAMPWROK
LAN_PHY_PWR_
CTRL / GPIO12
PLTRST#
PWRBTN#
PWROK
RI#
RSMRST#
SLP_A#
64
Type
DRAM Power OK: This signal should connect to the processor's
SM_DRAMPWROK pin. The PCH asserts this pin to indicate when
OD O
DRAM power is stable.
This pin requires an external pull-up
LAN PHY Power Control: LAN_PHY_PWR_CTRL should be
connected to LAN_DISABLE_N on the PHY. PCH will drive
LAN_PHY_PWR_CTRL low to put the PHY into a low power state
when functionality is not needed.
O
NOTES:
1. LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is
deasserted.
2. Signal can instead be used as GPIO12.
Platform Reset: The PCH asserts PLTRST# to reset devices on the
platform (such as SIO, FWH, LAN, processor, etc.). The PCH
asserts PLTRST# during power-up and when S/W initiates a hard
O reset sequence through the Reset Control register (I/O Register
CF9h). The PCH drives PLTRST# active a minimum of 1 ms when
initiated through the Reset Control register (I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.
Power Button: The Power Button will cause SMI# or SCI to
indicate a system request to go to a sleep state. If the system is
already in a sleep state, this signal will cause a wake event. If
PWRBTN# is pressed for more than 4 seconds, this will cause an
I
unconditional transition (power button override) to the S5 state.
Override will occur even if the system is in the S1-S4 states. This
signal has an internal pull-up resistor and has an internal 16 ms
de-bounce on the input. This signal is in the DSW well.
Power OK: When asserted, PWROK is an indication to the PCH
that all of its core power rails have been stable for 10 ms. PWROK
can be driven asynchronously. When PWROK is negated, the PCH
asserts PLTRST#.
NOTES:
I 1. It is required that the power rails associated with PCI/PCIe
typically the 3.3 V, 5 V, and 12 V core well rails) have been
valid for 99 ms prior to PWROK assertion in order to comply
with the 100 ms PCI 2.3/PCIe 1.1 specification on PLTRST#
deassertion.
2. PWROK must not glitch, even if RSMRST# is low.
Ring Indicate: This signal is an input from a modem. It can be
I enabled as a wake event, and this is preserved across power
failures.
Resume Well Reset: This signal is used for resetting the resume
power plane logic. This signal must be asserted for at least t201
I
after the suspend power wells are valid. When deasserted, this
signal is an indication that the suspend power wells are stable.
SLP_A#: Used to control power to the active sleep well (ASW) of
O
the PCH.
Signal Description
Description
Datasheet