Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 467

LPC Interface Bridge Registers (D31:F0)
13.1.31 BIOS_DEC_EN1—BIOS Decode Enable
Register (LPC I/F—D31:F0)
Offset Address: D8h
Default Value:
Bit
15
14
13
12
11
10
9
8
Datasheet
D9h
–
FFCFh
BIOS_F8_EN — RO. This bit enables decoding two 512-KB BIOS memory ranges, and
one 128-KB memory range.
0 = Disable
1 = Enable the following ranges for the BIOS
FFF80000h – FFFFFFFFh
FFB80000h – FFBFFFFFh
BIOS_F0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS:
FFF00000h – FFF7FFFFh
FFB00000h – FFB7FFFFh
BIOS_E8_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS:
FFE80000h – FFEFFFFh
FFA80000h – FFAFFFFFh
BIOS_E0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS:
FFE00000h – FFE7FFFFh
FFA00000h – FFA7FFFFh
BIOS_D8_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS
FFD80000h – FFDFFFFFh
FF980000h – FF9FFFFFh
BIOS_D0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS
FFD00000h – FFD7FFFFh
FF900000h – FF97FFFFh
BIOS_C8_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS
FFC80000h – FFCFFFFFh
FF880000h – FF8FFFFFh
BIOS_C0_EN — R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
1 = Enable the following ranges for the BIOS
FFC00000h – FFC7FFFFh
FF800000h – FF87FFFFh
Attribute: R/W, RO
Size: 16 bits
Description
467