Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 659

EHCI Controller Registers (D29:F0, D26:F0)
16.1.32 FLR_CID—Function Level Reset Capability ID
(USB EHCI—D29:F0, D26:F0)
Address Offset:
Default Value:
Function Level Reset: No
Bit
Capability ID — RO.
7:0 13h = If FLRCSSEL = 0
09h (Vendor Specific Capability) = If FLRCSSEL = 1
16.1.33 FLR_NEXT—Function Level Reset Next Capability Pointer
(USB EHCI—D29:F0, D26:F0)
Address Offset:
Default Value:
Function Level Reset: No
Bit
7:0 A value of 00h in this register indicates this is the last capability field.
16.1.34 FLR_CLV—Function Level Reset Capability Length and
Version
(USB EHCI—D29:F0, D26:F0)
Address Offset:
Default Value:
Function Level Reset: No
When FLRCSSEL = 0, this register is defined as follows:
Bit
15:10 Reserved.
FLR Capability — R/WO.
9
1 = Support for Function Level Reset (FLR).
TXP Capability — R/WO.
8 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is
Capability Length — RO. This field indicates the # of bytes of this vendor specific
7:0 capability as required by the PCI specification. It has the value of 06h for the FLR
capability.
When FLRCSSEL = 1, this register is defined as follows:
Bit
Vendor Specific Capability ID — RO. A value of 2h in this field identifies this
15:12
capability as Function Level Reset.
11:8 Capability Version — RO. This field indicates the version of the FLR capability.
Capability Length — RO. This field indicates the # of bytes of this vendor specific
7:0 capability as required by the PCI specification. It has the value of 06h for the FLR
capability.
Datasheet
98h
09h
99h
00h
9Ah–9Bh
2006h
supported.
Attribute: RO
Size: 8 bits
Description
Attribute: RO
Size: 8 bits
Description
Attribute: R/WO, RO
Size: 16 bits
Description
Description
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