Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 560

14.1.16.2 When SCC is 01h
When the programming interface is IDE, the register becomes an I/O BAR allocating
16 bytes of I/O space for the I/O-mapped registers defined in
although 16 bytes of locations are allocated, only 8 bytes are used as SINDX and
SDATA registers; with the remaining 8 bytes preserved for future enhancement.
Address Offset: 24h
Default Value:
Bit
31:16 Reserved
15:4 Base Address (BA) — R/W. Base address of the I/O space.
3:1 Reserved
0 Resource Type Indicator (RTE) — RO. Indicates a request for I/O space.
14.1.17 SVID—Subsystem Vendor Identification Register
(SATA–D31:F2)
Address Offset: 2Ch
Default Value:
Lockable:
Function Level Reset: No
Bit
Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware
15:0
action taken on this value.
14.1.18 SID—Subsystem Identification Register (SATA–D31:F2)
Address Offset: 2Eh
Default Value:
Lockable:
Function Level Reset: No
Bit
Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on
15:0
this value.
14.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2)
Address Offset: 34h
Default Value:
Bit
Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer
7:0 offset is 80h. This value changes to 70h if the Sub Class Code (SCC) (Dev 31:F2:0Ah) is
configure as IDE mode (value of 01).
560
27h
–
00000001h
2Dh
–
0000h
No
2Fh
–
0000h
No
80h
SATA Controller Registers (D31:F2)
Section
Attribute: R/WO
Size: 32 bits
Description
Attribute: R/WO
Size: 16 bits
Power Well: Core
Description
Attribute: R/WO
Size: 16 bits
Power Well: Core
Description
Attribute: RO
Size: 8 bits
Description
14.2. Note that
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