Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 553

SATA Controller Registers (D31:F2)
14.1.1 VID—Vendor Identification Register (SATA—D31:F2)
Offset Address: 00h
Default Value:
Lockable:
Bit
15:0
14.1.2 DID—Device Identification Register (SATA—D31:F2)
Offset Address: 02h
Default Value:
Lockable:
Bit
15:0
14.1.3 PCICMD—PCI Command Register (SATA–D31:F2)
Address Offset: 04h
Default Value:
Bit
15:11
10
9
8
7
6
5
4
3
2
1
0
Datasheet
01h
–
8086h
No
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
03h
–
See bit description
No
Device ID — RO. This is a 16-bit value assigned to the PCH SATA controller.
NOTE: The value of this field will change dependent upon the value of the MAP
Register. See Section 14.1.30
05h
–
0000h
Reserved
Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no
effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not
enabled.
1 = Internal INTx# messages will not be generated.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is
detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W. This bit controls the SATA controller's ability to act
as a master for data transfers. This bit does not impact the generation of completions
for split transaction commands.
Memory Space Enable (MSE) — R/W / RO. Controls access to the SATA controller's
target memory space (for AHCI). This bit is RO 0 when not in AHCI/RAID modes.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as
well as the Bus Master I/O registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
Attribute: RO
Size: 16 bit
Power Well: Core
Description
Attribute: RO
Size: 16 bit
Power Well: Core
Description
Attribute: RO, R/W
Size: 16 bits
Description
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