Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 791

PCI Express* Configuration Registers
19.1.51 RPDCGEN—Root Port Dynamic Clock Gating Enable
(PCI Express—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: E1h
Default Value:
Bits
7:4 Reserved. RO
Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — R/W.
0 = Disables dynamic clock gating of the shared resource link clock domain.
3 1 = Enables dynamic clock gating on the root port shared resource link clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5–8.
Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) — R/W.
0 = Disables dynamic clock gating of the shared resource backbone clock domain.
1 = Enables dynamic clock gating on the root port shared resource backbone clock
2
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5–8.
Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) — R/W.
1
0 = Disables dynamic clock gating of the root port link clock domain.
1 = Enables dynamic clock gating on the root port link clock domain.
Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) — R/W.
0
0 = Disables dynamic clock gating of the root port backbone clock domain.
1 = Enables dynamic clock gating on the root port backbone clock domain.
19.1.52 PECR1—PCI Express* Configuration Register 1
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: E8h–EBh
Default Value:
Bit
31:2
1
0
Datasheet
00h
domain.
00000020h
Reserved
PECR1 Field 2 — R/W. BIOS may set this bit to 1.
Reserved.
Attribute: R/W
Size: 8-bits
Description
Attribute: R/W
Size: 32 bits
Description
791