Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 538

13.9.6 TCO1_CNT—TCO1 Control Register
I/O Address:
Default Value:
Lockable:
Bit
15:13 Reserved
TCO_LOCK — R/WLO. When set to 1, this bit prevents writes from changing the
TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it
12
can not be cleared by software writing a 0 to this bit location. A core-well reset is
required to change this bit from 1 to 0. This bit defaults to 0.
TCO Timer Halt (TCO_TMR_HLT) — R/W.
0 = The TCO Timer is enabled to count.
1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will
11
10 Reserved
NMI2SMI_EN — R/W.
0 = Normal NMI functionality.
1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent
9
NMI_NOW — R/WC.
0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear
8
1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force
7:0 Reserved
538
TCOBASE +08h
0000h
No
cause an SMI# or set the SECOND_TO_STS bit. When set, this bit will prevent
rebooting and prevent Alert On LAN event messages from being transmitted on the
SMLink (but not Alert On LAN* heartbeat messages).
upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the
following table:
NMI_EN GBL_SMI_EN
0b 0b
0b 1b
1b 0b
1b 1b
this bit. Another NMI will not be generated until the bit is cleared.
an entry to the NMI handler.
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well: Core
Description
Description
No SMI# at all because GBL_SMI_EN = 0
SMI# will be caused due to NMI events
No SMI# at all because GBL_SMI_EN = 0
No SMI# due to NMI because NMI_EN = 1
R/W, R/WLO, R/WC
16-bit
Datasheet