Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 430

11.1.23 BPC—Bridge Policy Configuration Register
(PCI-PCI—D30:F0)
Offset Address: 4Ch–4Fh
Default Value:
Bit
31:30 Reserved
Subtractive Decode Compatibility Device ID (SDCDID) — R/W: When '0', this
function shall report a Device ID of 244Eh for desktop. When set to '1', this function
shall report the device Device ID value assigned to the PCI-to-PCI Bridge in
29
If subtractive decode (SDE) is enabled, having this bit as '0' allows the function to
present a Device ID that is recognized by the OS.
Subtractive Decode Enable (SDE) — R/W:
0 = Subtractive decode is disabled this function and will only claim transactions
28
1 = The subtractive decode policy as listed in SDP below applies.
Software must ensure that only one PCH device is enabled for Subtractive decode at a
time.
27:14 Reserved
Upstream Read Latency Threshold (URLT) — R/W: This field specifies the number
of PCI clocks after internally enqueuing an upstream memory read request at which
point the PCI target logic should insert wait states in order to optimize lead-off latency.
When the master returns after this threshold has been reached and data has not
arrived in the Delayed Transaction completion queue, then the PCI target logic will
insert wait states instead of immediately retrying the cycle. The PCI target logic will
insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or
STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived
13:8
yet).
Note that the starting event for this Read Latency Timer is not explicitly visible
externally.
A value of 0h disables this policy completely such that wait states will never be inserted
on the read lead-off data phase.
The default value (12h) specifies 18 PCI clocks (540 ns) and is approximately 4 clocks
less than the typical idle lead-off latency expected for desktop PCH systems. This value
may need to be changed by BIOS, depending on the platform.
430
10001200h
positively.
PCI-to-PCI Bridge Registers (D30:F0)
Attribute: R/W
Size: 32 bits
Description
Section .
Datasheet